module reg_8d_en(reset, en, clk, D, Q, Qb);

input  reset;
input  en;
input  clk;
inout wire  D  [7:0];
output wire Q  [7:0];
output wire Qb [7:0];

reg val[7:0];

wire din[7:0];

reg_8d inst(
    .clk(clk),
    .reset(reset),
    .d(din),
    .q(val),
);

assign Q = q_out;
assign Qb = ~q_out;

always @ (posedge clk) 
begin
    val <= 
    if (en == 1) d <= D;
end

endmodule
